1. Field of the Invention
The invention relates generally to the field of semiconductor integrated circuits, and more particularly, to systems and methods for a high-speed dynamic data bus.
2. Background Information
A data bus is a collection of wires that are primarily used to transmit data from one location to another. They are found in electronic devices such as computers, integrated circuit devices (e.g. integrated circuits), personal digital assistants, cellular telephones, and other similar devices. A data bus makes up half of what is generally referred to as the internal bus for an electronic device. The other half of an internal bus is an address bus, which is used to transfer information about where the data should go.
Typically, data is represented on a data bus in the form of binary digits, also known as bits. Each bit in turn represents only one of two values, a “0” (also referred to as an “off”), or a “1” (also referred to as an “on”). These two values are physically represented on the data bus in the form of electrical signals. A low voltage signal, ideally at zero volts, corresponds to the “0”, while a high voltage signal, ideally at the power supply voltage, corresponds to the “1”. In the current state-of-the-art, the power supply voltage can be around 3.3 volts for systems such as a computer motherboard, and around 1.8 volts for systems such as integrated circuit devices. In this description, these low voltage and high voltage signals are also referred to simply as “low signals” and “high signals.”
In an integrated circuit device, a data bus can couple a plurality of devices, such as data banks or memory banks, to a plurality of input/output (I/O) buffers. These I/O buffers in turn are part of an electrical pathway that eventually leads outside the integrated circuit device to a device such as a computer motherboard. Therefore, when data needs to be transmitted from a data bank to any other part of the computer, the data travels out of the data bank (in the form of bits) through a bit line, across the data bus, and then out an I/O buffer. And when data needs to be transmitted into a data bank on the chip, the data comes in from an I/O buffer, travels across the data bus, and then goes into the data bank though a bit line. High and low signals that represent actual data moving between data banks and I/O buffers are referred to herein as high and low “data signals.” All other electrical signals are referred to simply as “signals.”
FIG. 1 illustrates a simplified data bus architecture on a integrated circuit device as described above. Here, a two-bit data bus 100 (i.e. composed of two wires) connects four data banks 102, 104, 106, and 108 to two I/O buffers 114. Data banks 102–108 represent any and all devices that can be used in conjunction with a data bus, including but not limited to memory banks (e.g. RAM or ROM) or processors. Each data bank in this architecture is coupled to two bit lines 110 for transmitting data. It should be noted that many more lines for carrying data are typically used, and FIG. 1 shows only two lines for clarity. In the current state-of-the-art, data buses can easily have 128 lines (a 128-bit data bus) or more, data banks can have 128 or more bit lines, and integrated circuit devices can have numerous I/O buffers 114. It should also be noted that the term “line” as used in this description refers to any form of wire or connection that can carry electrical signals.
As shown in FIG. 1, bit lines 110 are connected to data bus 100 through tri-state buffers 112, which provide the energy required to drive data signals from bit lines 110 to I/O buffers 114 across data bus 100. To drive a data signal means to move a data signal from one location to another. Enable signals (labeled as “EN” in FIG. 1) are used to control tri-state buffers 112 by enabling or disabling this driving function. Using tri-state buffers in data bus architectures for driving data signals from data banks to I/O buffers is well known and is a standard practice.
Tri-state buffers 112 drive high data signals from data banks 102–108 to I/O buffers 114 by providing current to charge data bus 100 up to a high voltage level. Due to electrical resistance and/or capacitance in data bus 100, a significant amount of time may be required for the driving tri-state buffer 112 to charge data bus 100 from around zero volts (which is the starting voltage level for data bus 100) up to a voltage level that can be sensed or detected as a high data signal by an I/O buffer 114. This time is increased if the specific I/O buffer 114 that is receiving the high data signal is physically located far away from the driving tri-state buffer 112. This situation can be understood by a comparison of the time required for data bank 102 versus the time required for data bank 108. Data bank 108 is physically located near I/O buffers 114, whereas data bank 102 is physically located far from I/O buffers 114. Consequently, the driving tri-state buffers 112 for data bank 108 require less time to charge data bus 100 up to a level sufficient for detection by I/O buffers 114 than the driving tri-state buffers 112 for data bank 102. The reason for the greater amount of time required by the driving tri-state buffers of data bank 102 is that these driving tri-state buffers 112 must charge a longer portion of data bus 100. All of this time acts to lower the response time of data bus 100, resulting in slower system performance.
The use of a tri-state scheme to drive data signals from data banks to I/O buffers therefore suffers from limitations. The loading is larger on a tri-state buffer, and a significant amount of time may be required for a tri-state buffer to charge a data bus. Accordingly, there is a need for a faster and more dynamic way to drive data signals from data banks to I/O buffers.